1. Field of the Invention
The present invention relates to the design of on-chip circuitry for testing semiconductor chips. More specifically, the present invention relates to a method and an apparatus for performing voltage sampling on a semiconductor chip over an extended voltage range.
2. Related Art
On-chip samplers have been used to perform non-invasive probing of voltages on a semiconductor chip. This type of non-invasive probing is advantageous because it can significantly reduce the time required to test and debug a semiconductor chip. For example, FIG. 1 illustrates a simple on-chip sampler design. In FIG. 1, pass transistors M1 and M2 function as analog “flip-flops” which sample a voltage under test and present a modified version of the voltage to the gate of amplifying transistor M3. Amplifying transistor M3 converts this voltage into a current, which is multiplied and sent off-chip to a measuring device, such as an oscilloscope.
In order to calibrate the sampler's input-voltage-to-output-current conversion function, a separate gate M4 communicates an external calibration voltage to the amplifying transistor M3. This external calibration voltage produces a corresponding output, which is used to calibrate the input-voltage-to-output-current function.
During a subsequent voltage measurement operation, the analog flip-flop formed by pass transistors M1 and M2 can be clocked at a slightly different frequency from the chip clock, thereby causing the circuit to sample the on-chip waveform at a slightly different time offset for each cycle of an input signal. If performed properly, this sub-sampling technique can cause the circuit to display a nearly exact replica of the on-chip voltage waveform, but with an expanded time-base.
Unfortunately, the circuit illustrated in FIG. 1 cannot easily sample on-chip voltages near the power supply voltage Vdd. This is because the NMOS pass gates M1 and M2 will turn off when the input voltage rises to within a threshold of the gate voltage for the pass gates (which is asserted as Vdd). One solution to this problem is to use a higher power supply voltage to drive the gates of nMOS devices M1 and M2. This allows the nMOS gates M1 and M2 to continue to conduct because their gate voltages exceed any on-chip voltage being tested. Although this scheme can be made to work, the higher gate voltages can possibly destroy the gates. The risk of gate destruction can be greatly reduced by using thick-oxide I/O devices. Unfortunately, such thick-oxide I/O devices are slow, which can significantly reduce the bandwidth of the sampler. Another disadvantage is that an extra pin is required for the higher supply voltage, which involves additional expense. Moreover, routing the extra supply voltage around the chip can significantly increase routing complexity.
Hence, what is needed is a method and an apparatus for sampling on-chip voltages without the problems described above.